Operational amplifiers in negative feedback arrangements are common circuit elements in analog integrated circuits. An ideal integrator circuit has infinite DC gain and a constant phase of -90.degree.. However, due to non-idealities, these circuits have a finite gain and a phase shift which is different from -90.degree. (henceforth called phase error). In particular, parasitic input and output capacitances introduce a extra poles in the transfer equation which produces unacceptable phase errors if the pole is too close to the unity gain frequency of the integrator.
This problem becomes particularly acute for high frequency applications which are implemented using MOS technologies. This is because the op-amps built using these technologies are usually single-stage circuits that are built with MOSFETS which have a limited transconductance. This limitation reduces the frequency of the parasitic pole.
A conventional feedback circuit is illustrated in FIGS. 1a and 1b. The circuit 10 comprises an operational amplifier 12 having trans-conductance g.sub.m and a transconductance amplifier 14 having trans-conductance G.sub.m. Ideally, the transconductance amplifier 14 sources (or sinks) an output current equal to G.sub.m V.sub.in. A transconductance amplifier 14 is used instead of the more conventional resistor to ensure adequate DC gains for the integrator, which is the cascaded gains of the transconductor and the opamp. A feedback impedance 16 of magnitude Y is connected between the inputs and outputs of the op-amp 12. Also illustrated are the parasitic input and output capacitances C.sub.pi 18 and C.sub.po 20, respectively.
The frequency domain transfer function for this circuit 10 can be written as: ##EQU1##
The first term in the equation represents the transfer function for an ideal op-amp 12. The second term is a result of the non-ideal input and output capacitances combined with a non-infinite g.sub.m. Because of the difference in sign between the numerator and denominator of the non-ideal equation component and the non-infinite g.sub.m, the phase error terms of the pole and zero do not cancel and a net negative phase error is produced. The lower the value of g.sub.m, the more significant the error introduced by these terms, and thus the more significant the impact of the pole/zero on the performance of this circuit and other circuits which include a similar feedback circuit design.
Because of the feedback loop, the op-amp 12 must generate the same current as provided by the transconductance amplifier 14. In addition, opamp 12 must also generate current to account for the current drawn by the parasitic capacitances. With reference to the current flows illustrated in FIG. 1b, the op-amp 12 must source an output current I.sub.O =I.sub.F +I.sub.PO, where I.sub.PO is the current flow through the parasitic output capacitance C.sub.PO 20. Further, there is also an induced voltage V.sub.PI, at the input to the op-amp 12, which produces an additional current I.sub.PI. Thus, I.sub.F =G.sub.m V.sub.IN +I.sub.PI. In other words, some of the output current is "stolen" to supply the parasitic input and output capacitances, This difference results in detriments, such as phase error, which impact the performance of the circuit.
Various techniques have been employed to reduce the errors caused by these non-idealities. In one variation, a resistance is introduced in series with the feedback impedance 16. This provides some improvement at low frequencies, but is not particularly effective in high frequency situations. Alternative configurations make use of error detection devices which measure the output of the op-amp and adjust various circuit parameters by means of a control signal to compensate for the unwanted phase-shift. However, this technique can be cumbersome and requires relatively complex error detection and adaptive circuitry.
One particular solution for the case when the feedback impedance is a capacitor used for the purpose of Miller-compensating a transconductance stage has been implemented using a Multipath Miller Cancellation technique, such as described in U.S. Pat. No. 5,485,121 and discussed in R. Eschauzier and J. Huijsing, "An Operational Amplifier with Miller-Zero cancelation for RHP zero removal", ESSCIRC'93, European Solid-state Circuits Conference 1993, pp.122-125. This technique provides a parallel current path which is configured to bypass the Miller-compensated transductance stage and provide a current which compensates for the current directly passing through the Miller capacitor. However, the solution presented is restricted to Miller-compensated amplifiers and does not generally address the problems created by non-ideal amplifiers in negative feedback configurations with non-capacitive impedances.
An alternative solution is to introduce a unity-gain buffer 22 in the feedback loop between the output of the op-amp 12 and the impedance 16, such as shown in FIG. 1c. The purpose of the buffer 22 is to supply the feedback current G.sub.m V.sub.IN instead of the op-amp 22 and thereby avoid introducing a voltage differential at the input of the op-amp 12 which results in a current drain into the parasitic input capacitance. However, the buffer 22 has a finite output impedance R.sub.O 24. Thus, the transfer function of this circuit is: ##EQU2##
The first term in Equation 2 is the ideal behavior. The second term represents the error which results from the non-ideality of the buffer 22. In particular, the current G.sub.m V.sub.IN produced by buffer 22 is forced to flow through the output impedance R.sub.O 24 as well as the feedback impedance 16. Thus, there is a voltage drop in the feedback path which degrades the performance of the circuit. Although the buffer 22 could be designed to have a very small output impedance, such a buffer would require substantially more power than is generally available for high-frequency, low power devices.
Accordingly, it would be advantageous to provide a generalized op-amp feedback circuit structure with compensation for input and output capacitances.
It would also be advantageous to provide an improved unity-gain buffered feedback circuit with compensation for the output resistance of the feedback buffer.